1. Field of the Invention
The embodiments of the invention generally relate to testing methods and, more particularly, to taking parametric measurements during post-manufacture testing of chips in order to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes.
2. Description of the Related Art
Generally, semiconductor chips (i.e., semiconductor products, dies, integrated circuit devices, etc.) are produced by using known processing techniques to form multiple identical products on the same wafer. Deviations in parametric measurements from what is assumed during design, either in different areas across the wafer and/or within different areas across individual chips, impact semiconductor product function in customer applications. However, parametric deviations are typically not measured post manufacture (i.e., during wafer-level testing, module-level testing, burn-in level testing, etc.), but rather are only measured during in-line testing. Unfortunately, for a number of reasons, the parametric measurements taken during in-line testing cannot readily be used to disposition semiconductor products during final testing. Additionally, for a number of reasons, these in-line parametric measurements can also not readily be used to identify parametric impact on product yield. Therefore, there is a need in the art for a testing method in which, during final testing, various electrical and physical parametric measurements are taken and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes.